Publications

  1. LeBeane, M.; Potter, B.; Pan, A.; Dutu, A.; Agarwala ,V.; Lee, W.; Majeti, D.; Ghimre, B.; Van Tassell, E.; Wasmundt, S,; Benton, B.; Breternitz, M; Thottethodi, M; John, L.K; Reinhardt, S. K., “Extended Task Queuing: Active Messages for Heterogeneous Systems,”, Accepted in the International Conference for High Performance Computing, Networking, Storage and Analysis (SC’16).
  2. Abhisek Pan and Vijay S. Pai, “Runtime-Driven Shared Last-Level Cache Management for Task-Parallel Programs”, The International Conference for High Performance Computing, Networking, Storage, and Analysis, SC15, November, 2015.
  3. Abhisek Pan and Vijay S. Pai, “Runtime-Driven Shared Last-Level Cache Management for Task-Parallel Programs”, Department of Electrical and Computer Engineering Technical Report, Purdue University, http://docs.lib.purdue.edu/ecetr/466.
  4. Abhisek Pan, Rance Rodrigues, and Sandip Kundu, “A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors”, The ACM Transactions on Embedded Computing Systems, Volume 14, Issue 1, January 2015.
  5. Vivek Joy Kozhikkottu, Abhisek Pan, Vijay Pai, Sujit Dey, Anand Raghunathan, “Variation Aware Cache Partitioning for Multithreaded Programs”, The 51st Design Automation Conference (DAC-51), June 2014.
  6. Abhisek Pan and Vijay S. Pai, “Imbalanced Cache Partitioning for Balanced Data-Parallel Programs”, The 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46), December 2013. [paper slides]
  7. Abhisek Pan, John Paul Walters, Vijay S. Pai, Dong-In D. Kang, Stephen P. Crago, “Integrating High Performance File Systems in a Cloud Computing Environment“, The International Workshop on Data-Intensive Scalable Computing Systems (DISCS), in conjunction with the 2012 ACM/IEEE Supercomputing Conference (SC’12), November 2012.
  8. Pan, A.; Khan, O.; Kundu, S., “Improving Yield and Reliability of Chip Multiprocessors”, Design, Automation and Test in Europe (DATE), April 2009.
  9. Sanyal A.; Pan, A.; Kundu, S., “A Study on Impact of Aggressor Derating in the Context of Multiple Crosstalk Effects in Integrated Circuits”, The 19th ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2009.
  10. Sanyal A.; Pan, A.; Kundu, S., “A Study on Impact of Loading Effect on Capacitive Crosstalk Noise”, 10th International Symposium on Quality of Electronic Design (ISQED) pp.696-701, 2009.
  11. Pan, A.; Tschanz, J.W.; Kundu, S., “A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits,” 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Oct.

Masters Thesis:

  1. “A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors”, Pan A., Masters Theses, 327, University of Massachusetts, Amherst, September 2009. url: http://scholarworks.umass.edu/theses/327/.

Presentations:

  1. “Chapel-on-HSA: Towards Seamless Acceleration of Chapel Code using the Heterogeneous System Architecture,” Abhisek Pan and Mike Chu, The 3rd Annual Chapel Implementers and Users Workshop (CHIUW 2016), May 2016.
  2. “Runtime-driven Shared Last-level Cache Management for Task-parallel Programs,” Abhisek Pan, International Conference for High Performance Computing, Networking, Storage and Analysis (SC’15), November 2015.
  3. “Accelerating MPI Custom Reductions through the Heterogeneous System Architecture,” Abhisek Pan, AMD Booth Presentation, International Conference for High Performance Computing, Net- working, Storage and Analysis (SC’15), November 2015.
  4. “Imbalanced Cache Partitioning for Balanced Data-Parallel Programs,” 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 46), December 2013.
  5. “Integrating HPFS in a Cloud Computing Environment”, A. OpenStack Summit. San Diego, October 2012. Presented by Abhisek Pan and David Kang. (Link to Video.) B. The International Workshop on Data-Intensive Scalable Computing Systems, November 2012. 
  6. “A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits,” 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2008.